Field of the Invention
The invention relates to an arrangement and a method for disabling configuration or programming of a programmable hardware component, in particular of a PLD or a processor.
Description of the Background Art
PLDs, programmable logic devices, are integrated circuits using digital technology in which a logic circuit can be programmed or configured. To this end, the PLD has a configuration interface by which means the logic circuit in the PLD can be configured, thus, in concrete terms, defining the structural rules represented by the logic circuit for the basic functionality of individual universal blocks in the PLD and their connection to one another. PLDs include, in particular, FPGAs (field programmable gate arrays) and CPLDs (complex programmable logic devices).
Processors are integrated circuits using digital technology in which a logic circuit is largely hard-wired and in which a logic function can be programmed or configured by installing software. To this end, the processor has a configuration interface for installing software and for the manipulation of installed software.
In the following, a programmable hardware component can be understood to be, for example, a processor, a PLD, or a combination of the two. A logic can be understood to be, for example, a piece of software in a processor or a logic circuit in a PLD.
Oftentimes, programmable hardware components have, in addition to the configuration interface for configuring the hardware component, an additional debugging interface, which can be used primarily for debugging the logic programmed in the programmable hardware component, but which likewise permits configuration of the logic.
Also, some models have no separate configuration interface because the manufacturer only makes provision for configuration of the logic through the debugging interface. In this case it is possible to provide a separate configuration interface and a separate debugging interface by means of a circuit implemented outside of the hardware component. For example, the debugging interface can be connected to a switch that is set up to connect the debugging interface to a choice of a first external interface or a second external interface, wherein the first external interface is intended for programming the programmable hardware component, and the second external interface is made available to a user for debugging the logic programmed in the programmable hardware component, and wherein the switch is set up to connect the debugging interface to the first external interface during a programming process of the hardware component, and to connect the debugging interface to the second external interface when no programming process of the hardware component is taking place. For the invention it is unimportant whether a configuration interface and a debugging interface are each provided natively as a separate interface, or whether this is accomplished using a switch located outside of the hardware component.
Now if a configuration of the programmable hardware components by a user is to be disabled, an access by the user to the configuration interface can first be blocked. If the user is to have the option of debugging the logic of the programmable hardware component, however, the debugging interface must be enabled. But in the designs known from the prior art, however, this also means that the user not only can debug the programmable hardware component, but can also configure or program it.
In certain cases, programming of the programmable hardware component via the debugging interface is not desirable, however, such as when a first programmable hardware component, in particular an FPGA, is coupled to a second programmable hardware component, in particular a processor. An arrangement of this nature is known in the prior art, for example from computer systems for real time simulation of complex physical and electronic systems, where it allows the processor to pass certain computing processes, in particular especially time-critical computing processes, to the FPGA.
In an arrangement of this nature, it is useful to have configuration of the FPGA performed exclusively by the processor. A manufacturer of this type of computer system generally also offers a tool for configuration or programming of the computer system as a whole, including the FPGA coupled to the processor. During the course of programming the computer system, the processor will configure the coupled FPGA through a configuration interface, which is to say will write it with a logic. In addition to a part that is freely configurable by the user, this logic can also contain a mandatory interface logic, not configurable by the user or only configurable by the user to a limited degree, that governs the data exchange with the coupled processor in ongoing operation. In this way, defined communication behavior between the processor and the FPGA can be predetermined by the manufacturer of the computer system, and safety mechanisms against erroneous programming can be predetermined. Without these safety mechanisms, erroneous programming can result in erroneous behavior of the computer system, and in the worst case can even result in destruction of the FPGA or other installed hardware. The programmability of the FPGA through the debugging interface provides a possibility for circumventing these safety mechanisms. A programming access through the debugging interface causes overwriting of the entire logic present on the FPGA or at least of a selected subsection of its logic circuit, and in this way can also cause overwriting of the—actually mandatory—interface logic. For this reason, in the prior art the debugging interface in computer systems such as the one described above generally is not accessible to the user. As a result, however, it is also not possible for the user to use the debugging interface for purposes other than programming of the FPGA, for example for monitoring variables for the purpose of debugging the FPGA logic.